Input Transitions for the Specified Gates (according to the implementations provided on the UVA ECE wiki) are as follows:

2-input NAND gate:
worst tphl: AB=10->11
worst tplh: AB=11->10

2-input NOR gate:
worst tphl: AB=00->10
worst tplh: AB=10->00

2-input AND gate:
worst tphl: AB=11->10
worst tplh: AB=10->11

2-input OR gate:
worst tphl: AB=10->00
worst tplh: AB=00->10

2-input XOR gate:
worst tphl: AB=01->11
worst tplh: AB=11->01

F2=(ABC+D(A+B+C))' gate:
worst tphl: ABCD=0001->1001
worst tplh: ABCD=1101->1100
